This invention relates to high voltage field effect transistors (FETs), and more particularly to a method of forming a high voltage FET having a relatively small ratio of channel width to channel length (W/L), and to an FET made using this method.
High voltage FETs are used in a wide variety of applications, most of which require the FET to handle relatively large currents. The ability to handle relatively large currents is a function of the ratio of the channel width to the channel length (W/L) of the FET, with high current handling ability indicated by a large W/L. All high voltage FETs, whether designed to handle large currents or not, share design features necessitated by high voltages. A typical design for a high voltage FET places an annular source in the major surface of a semiconductor substrate. Outside of the source is a channel stop that isolates the FET from other devices on the substrate. Inboard and in contact with the source is a gate. Inboard of the gate is a drift region with an overlying region of field oxide. Inboard of the drift region and the drift field oxide is a circular drain region, the center of the FET. The annular and circular shapes of the elements of the FET act to diffuse field lines. The FET can be either depletion mode or enhancement mode, depending on whether the channel is doped with the same impurity type as the source, drain and drift region (i.e., depletion mode), or whether the channel is of opposite type (i.e., enhancement mode).
A typical high voltage FET designed to handle large current will have an annular gate. Beneath the gate is a channel, which is separated from the gate by a gate insulator. The channel is the portion of the substrate controlled by the gate, and hence is annular like the gate above. The annular shape of the channel gives the device a relatively large W/L, since the length is the radial thickness of the gate, and the width is approximately the circumference of the gate. To make the annular channel, the annular gate is used to mask the implanting of impurities to form source and drain regions. In this manner, the source region, channel region and drain region are self-aligned.
The present designs of high voltage FETs have generally proven adequate, as have the methods of making them. However, the designs and methods are optimized for FETs that handle relatively large current.